Patent · US Active

Methods of forming isolation material on FinFET semiconductor devices and the resulting devices

US9064890B1 · kind B1 · utility

16Cited by
2References
18Claims
0Family size

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Key dates

Filing dateMar 24, 2014
Grant dateJun 23, 2015
Priority date
Expiry dateMar 24, 2034

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D84/0167

Abstract

One method disclosed includes, among other things, forming an initial fin, covering a top surface and a portion of the sidewalls of the initial fin structure with etch stop material, forming a sacrificial gate structure above and around the initial fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, performing at least one process operation to remove the sacrificial gate structure and thereby define a replacement gate cavity, performing at least one etching process through the replacement gate cavity to remove a portion of the initial fin structure so as to thereby define a final fin structure and a channel cavity positioned below the final fin structure, and substantially filling the channel cavity with an insulating material.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.