Method for producing a field effect transistor with implantation through the spacers
US9070709B2 · kind B2 · utility
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6References
15Claims
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Key dates
| Filing date | Jun 9, 2011 |
| Grant date | Jun 30, 2015 |
| Priority date | — |
| Expiry date | Jun 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The substrate successively includes a support substrate, an electrically insulating layer, a semiconductor material layer, and a gate pattern. The semiconductor material layer and gate pattern are covered by a covering layer. A first doping impurity is implanted in the semiconductor material layer through the covering layer so as to place the thickness of maximum concentration of the first doping impurity in the first layer. The covering layer is partly eliminated so as to form lateral spacers leaving source/drain electrodes free.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.