Use of etch process post wordline definition to improve data retention in a flash memory device

US9082714B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Randy J. Koval · Boise, US
• Max Hineman · Boise, US
• Ronald A. Weimer · Boise, US
• Vinayak Shamanna · Boise, US
• Thomas M. Graettinger · Boise, US
• William Kueber · Boise, US
• Christopher J. Larsen · Boise, US
• Alex J. Schrinsky · Boise, US

Key dates

• Filing date: Sep 22, 2011
• Grant date: Jul 14, 2015
• Expiry date: Sep 22, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/685
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments of the present disclosure are directed towards use of an etch process post wordline definition to improve data retention in a flash memory device. In one embodiment, a method includes forming a plurality of wordline structures on a substrate, wherein individual wordline structures of the plurality of wordline structures include a control gate having an electrically conductive material and a cap having an electrically insulative material formed on the control gate, depositing an electrically insulative material to form a liner on a surface of the individual wordline structures, and etching the liner to remove at least a portion of the liner. Other embodiments may be described and/or claimed.