Methods of forming gate structures for transistor devices for CMOS applications

US9105497B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Zhendong Hong · San Jose, US
• Susie Tzeng · Fremont, US
• Amol Joshi · Sunnyvale, US
• Ashish Bodke · San Jose, US
• Divya Pisharoty · Fremont, US
• Usha Raghuram · Saratoga, US
• Olov Karlsson · San Jose, US
• Kisik Choi · Hopewell Junction, US
• Salil Mujumdar · San Jose, US
• Paul R. Besser · Sunnyvale, US
• Jinping Liu · Ballston Lake, US
• Hoon Kim · Suwon-si, KR

Key dates

• Filing date: Sep 4, 2013
• Grant date: Aug 11, 2015
• Expiry date: Sep 4, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/85
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.