Methods of forming transistor devices with different threshold voltages and the resulting products
US9178036B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2014 |
| Grant date | Nov 3, 2015 |
| Priority date | — |
| Expiry date | Sep 22, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One illustrative method disclosed herein includes, among other things, performing at least one recess etching process such that a first portion of a high-k oxide gate insulation layer and a first portion of a metal oxide layer is positioned entirely within a first gate cavity and a second portion of the high-k oxide gate insulation layer, a conformal patterned masking layer and a second portion of the metal oxide layer is positioned entirely within a second gate cavity, performing at least one heating process to form a composite metal-high-k oxide alloy gate insulation layer in the first gate cavity, while preventing metal from the metal oxide material from being driven into the second portion of the high-k oxide gate insulation layer in the second gate cavity during the at least one heating process, and forming gate electrode structures in the gate cavities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.