Transistor contacts self-aligned in two dimensions
US9202751B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2014 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Jul 1, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.