Engineered substrate and device for co-integration of strained silicon and relaxed silicon
US9209065B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2014 |
| Grant date | Dec 8, 2015 |
| Priority date | — |
| Expiry date | Sep 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02658
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A strained silicon material layer is bonded to a relaxed silicon material layer. The strained silicon material and any defect containing region formed during bonding are completely removed from a second device region, while a portion of the strained silicon material layer remains in a first device region. A relaxed silicon material portion is epitaxially formed on an exposed portion of the relaxed silicon material layer. A high performance nFET device, in which leakage is not a main concern, can be formed on the remaining portion of the strained silicon material layer in the first device region, and a pFET device or a low leakage nFET device can be formed on the epitaxially formed relaxed silicon material portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.