Inventor · Mount Kisco, NY, US

Darsen D. Lu

40Patents
5h-index
23Co-inventors
65Inventor score

Filing activity: Mar 12, 2013 → Dec 22, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US9525027B2 Lateral bipolar junction transistor having graded SiGe base Electricity 11 Active
US9786737B2 FinFET with reduced parasitic capacitance Electricity 8 Active
US9548386B1 Structure and method for compressively strained silicon germanium fins for pFET devices and tensily strained silicon fins for nFET devices Electricity 7 Active
US9455250B1 Distributed decoupling capacitor Electricity 7 Active
US9583492B2 Structure and method for advanced bulk fin isolation Electricity 5 Active
US9299618B1 Structure and method for advanced bulk fin isolation Electricity 5 Active
US9653541B2 Structure and method to make strained FinFET with improved junction capacitance and low leakage Electricity 3 Active
US9543323B2 Strain release in PFET regions Electricity 2 Active
US9583624B1 Asymmetric finFET memory access transistor Electricity 2 Active
US9362400B1 Semiconductor device including dielectrically isolated finFETs and buried stressor Electricity 2 Active
US9553173B1 Asymmetric finFET memory access transistor Electricity 2 Active
US9276113B2 Structure and method to make strained FinFET with improved junction capacitance and low leakage Electricity 1 Active
US10177223B2 FinFET with reduced parasitic capacitance Electricity 1 Active
US10243042B2 FinFET with reduced parasitic capacitance Electricity 1 Active
US9954083B2 Semiconductor structures having increased channel strain using fin release in gate regions Electricity 1 Active
US9515171B1 Radiation tolerant device structure Electricity 1 Active
US10056474B2 Semiconductor structures having increased channel strain using fin release in gate regions Electricity 1 Active
US9034715B2 Method and structure for dielectric isolation in a fin field effect transistor Electricity 1 Active
US10892364B2 Dielectric isolated fin with improved fin profile Electricity 0 Active
US9564439B2 Structure and method for advanced bulk fin isolation Electricity 0 Active
US10262991B2 Distributed decoupling capacitor Electricity 0 Active
US9209065B1 Engineered substrate and device for co-integration of strained silicon and relaxed silicon Electricity 0 Active
US10347752B2 Semiconductor structures having increased channel strain using fin release in gate regions Electricity 0 Active
US10593663B2 Distributed decoupling capacitor Electricity 0 Active
US10734477B2 FinFET with reduced parasitic capacitance Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.