Uniaxially-strained FD-SOI finFET
US9252208B1 · kind B1 · utility
7Cited by
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20Claims
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Key dates
| Filing date | Jul 31, 2014 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Jul 31, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.