Methods of forming replacement gate structures for transistors and the resulting devices
US9257348B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 6, 2013 |
| Grant date | Feb 9, 2016 |
| Priority date | — |
| Expiry date | Dec 20, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are illustrative methods and devices that involve forming spacers with internally trimmed internal surfaces to increase the width of the upper portions of a gate cavity. In some embodiments, the internal surface of the spacer has a stepped cross-sectional configuration or a tapered cross-sectional configuration. In one example, a device is disclosed wherein the P-type work function metal for a PMOS device is positioned only within the lateral space defined by the untrimmed internal surfaces of the spacers, while the work function adjusting metal for the NMOS device is positioned laterally between the lateral spaces defined by both the trimmed and untrimmed internal surfaces of the sidewall spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.