Structure and method to make strained FinFET with improved junction capacitance and low leakage
US9276113B2 · kind B2 · utility
1Cited by
6References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2014 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | Mar 29, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0262
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device that includes forming a gate structure on a fin structure and etching the source and drain region portions of the fin structure to provide a recessed surface. A first semiconductor layer is formed on the recessed surface of the fin structure that is doped to a first conductivity type. A leakage barrier layer is formed on the first semiconductor layer. A second semiconductor layer is formed on the leakage barrier layer. The second semiconductor layer is doped to a second conductivity type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.