Methods of forming source/drain regions for a PMOS transistor device with a germanium-containing channel region
US9343300B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2015 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | Apr 15, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/2257
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure is directed to forming relatively abrupt junctions between the channel region and source/drain regions of a PMOS transistor device with a germanium-containing channel region. A liner layer is formed in previously formed source/drain cavities prior to the formation of epi semiconductor material in the source/drain cavities above the liner layer. The materials for the liner layer and, particularly, the concentration of germanium (if any is present) are adjusted relative to the germanium concentration in the channel region and the epi source/drain material such that, during an anneal process, dopant materials (e.g., boron) that diffuse from the source/drain region during the anneal process tend to accumulate in or near the liner layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.