Gate structures for transistor devices for CMOS applications and products

US9362283B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Zhendong Hong · San Jose, US
• Susie Tzeng · Fremont, US
• Amol Joshi · Sunnyvale, US
• Ashish Bodke · San Jose, US
• Divya Pisharoty · Fremont, US
• Usha Raghuram · Saratoga, US
• Olov Karlsson · San Jose, US
• Kisik Choi · Hopewell Junction, US
• Salil Mujumdar · San Jose, US
• Paul R. Besser · Sunnyvale, US
• Jinping Liu · Ballston Lake, US
• Hoon Kim · Suwon-si, KR

Key dates

• Filing date: Jul 7, 2015
• Grant date: Jun 7, 2016
• Expiry date: Jul 7, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/85
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer.