Semiconductor device including dielectrically isolated finFETs and buried stressor
US9362400B1 · kind B1 · utility
2Cited by
7References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2015 |
| Grant date | Jun 7, 2016 |
| Priority date | — |
| Expiry date | Mar 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/798
Abstract
A finFET semiconductor device includes a semiconductor-on-insulator (SOI) substrate including a buried insulator layer, a plurality of semiconductor fins on the buried insulator layer, and a gate structure covering the semiconductor fins, at least one buried stressor element embedded in the buried insulator layer, and a source/drain element on an upper surface of the at least one buried stressor element and integrally formed with at least one semiconductor fin among the plurality of semiconductor fins, the at least one buried stressor element applying a stress upon the source/drain element from therebeneath.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.