Alternate dual damascene method for forming interconnects
US9431292B1 · kind B1 · utility
3Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2015 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Apr 29, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1036
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
After forming at least one opening in a material stack comprising a sacrificial metal template layer overlying a first dielectric material layer, a sacrificial material portion is deposited in the at least one opening as a place holder for an interconnect structure later formed. Next, the sacrificial metal template layer is removed and a second dielectric material layer is formed to fill voids that were previously occupied by the sacrificial metal template layer. After removing the sacrificial material portion from the at least one opening, an interconnect structure is formed within the at least one opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.