Single spacer for complementary metal oxide semiconductor process flow

US9450095B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Marc A. Bergendahl · Troy, US
• Kangguo Cheng · Schenectady, US
• Jessica Dechene · Watervliet, US
• Fee Li Lie · Albany, US
• Eric R. Miller · Schenectady, US
• Jeffrey C. Shearer · Albany, US
• John R. Sporre · Albany, US
• Sean Teehan · Rensselaer, US

Key dates

• Filing date: Feb 4, 2016
• Grant date: Sep 20, 2016
• Expiry date: Feb 4, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/853
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of forming a semiconductor device that includes forming a high-k dielectric fin liner on the first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region, and forming a gate structure including a low-k dielectric gate sidewall spacer on the channel region of the first and second plurality of fin structures. A first epitaxial semiconductor material on the first plurality of fin structures from which the high-k dielectric fin liner has been removed. The first epitaxial semiconductor material is then oxidized, and a remaining portion of the high-k dielectric fin liner is removed. A second epitaxial semiconductor material is formed on the second plurality of fin structures.