Integrating enhancement mode depleted accumulation/inversion channel devices with MOSFETs
US9484452B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2014 |
| Grant date | Nov 1, 2016 |
| Priority date | — |
| Expiry date | Dec 10, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
Abstract
A plurality of gate trenches is formed into an epitaxial region of a first conductivity type over a semiconductor substrate. One or more contact trenches are formed into the epitaxial region, each between two adjacent gate trenches. One or more source regions of the first conductivity type are formed in a top portion of the epitaxial region between a contact trench and a gate trench. A barrier metal is formed inside each contact trench. Each gate trench is substantially filled with a conductive material separated from trench walls by a layer of dielectric material to form a gate. A heavily doped well region of a conductivity opposite the first type is provided in the epitaxial region proximate a bottom portion of each of the contact trenches. A horizontal width of a gap between the well region and the gate trench is about 0.05 μm to 0.2 μm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.