Local strain generation in an SOI substrate
US9502558B2 · kind B2 · utility
4Cited by
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9Claims
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Key dates
| Filing date | Jul 6, 2015 |
| Grant date | Nov 22, 2016 |
| Priority date | — |
| Expiry date | Jul 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Method to strain a channel zone of a transistor of the semiconductor on insulator type transistor that makes use of an SMT stress memorization technique in which regions located under the insulation layer of the substrate (FIG. 6) are amorphized, before the transistor gate is made.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.