Structure and method for advanced bulk fin isolation
US9583492B2 · kind B2 · utility
5Cited by
9References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2016 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | Mar 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by an epitaxial semiconductor stack is provided. The epitaxial semiconductor material stack that provides the isolation includes, from bottom to top, a semiconductor punch through stop containing at least one dopant of a conductivity type which differs from the conductivity type of the particular device region that the semiconductor fin is formed in, and a semiconductor diffusion barrier layer containing no n- or p-type dopant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.