FinFET device with channel strain
US9640640B1 · kind B1 · utility
3Cited by
1References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2016 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Apr 22, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device, the method comprises forming a fin on a substrate, forming a dummy gate stack on the fin and the substrate, removing a portion of an exposed portion of the fin, forming a source/drain region on an exposed portion of the fin, forming a conductive contact on the source/drain region, removing the dummy gate stack to expose a channel region of the fin, implanting ions in the channel region of the fin, performing an annealing process, and forming a gate stack on the channel region of the fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.