Interconnect structure with enhanced reliability

US9673089B2 · kind B2 · utility

Assignee

• AURIGA INNOVATIONS, INC · CA

Inventors

• Griselda Bonilla · Hopewell Junction, US
• Kaushik Chanda · Fishkill, US
• Robert D. Edwards · Marlboro, US
• Ronald G. Filippi · Wappingers Falls, US
• Andrew H. Simon · Fishkill, US
• Ping-Chuan Wang · Hopewell Junction, US

Key dates

• Filing date: Oct 31, 2014
• Grant date: Jun 6, 2017
• Expiry date: Jul 25, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided.