Threshold voltage and well implantation method for semiconductor devices
US9780002B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2016 |
| Grant date | Oct 3, 2017 |
| Priority date | — |
| Expiry date | Jun 6, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methodologies for patterning and implantation are provided Embodiments include forming fins; forming an SiN over the fins; forming an a-Si layer over the SiN; forming and patterning a first patterning layer over the a-Si layer; etching through the a-Si layer using the first patterning layer as a mask; removing the first patterning layer; implanting ions in exposed groups of fins; forming and patterning a second patterning layer to expose a first group of fins and a portion of the a-Si layer on opposite sides of the first group of fins; implanting ions in a first region of the first group of fins; forming a third patterning layer over the first region of the first group of fins and exposing a second region of the first group of fins; and implanting ions in the second region of the first group of fins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.