Integrating atomic scale processes: ALD (atomic layer deposition) and ALE (atomic layer etch)
US9805941B2 · kind B2 · utility
41Cited by
11References
26Claims
0Family size
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Key dates
| Filing date | Jan 6, 2017 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | Jan 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods are provided for integrating atomic layer etch and atomic layer deposition by performing both processes in the same chamber or reactor. Methods involve sequentially alternating between atomic layer etch and atomic layer deposition processes to prevent feature degradation during etch, improve selectivity, and encapsulate sensitive layers of a semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.