Structures to avoid floating RESURF layer in high voltage lateral devices

US9876071B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Yongxi Zhang · Plano, US
• Philip L. Hower · Concord, US
• John Lin
• Guru Mathur · Plano, US
• Scott Balster · Dallas, US
• Constantin Bulucea · Milpitas, US
• Zachary K. Lee · Fremont, US
• Sameer Pendharkar · Allen, US

Key dates

• Filing date: Feb 28, 2015
• Grant date: Jan 23, 2018
• Expiry date: Feb 28, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/516
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.