Dummy gate formation using spacer pull down hardmask

US9893166B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Marc A. Bergendahl · Troy, US
• Kangguo Cheng · Schenectady, US
• Fee Li Lie · Albany, US
• Eric R. Miller · Schenectady, US
• John R. Sporre · Albany, US
• Sean Teehan · Rensselaer, US

Key dates

• Filing date: Jun 6, 2017
• Grant date: Feb 13, 2018
• Expiry date: Jun 6, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/661
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Forming a dummy gate on a semiconductor device is disclosed. A first sacrificial layer is formed on a fin, and a second sacrificial layer is formed on the first sacrificial layer. A first hardmask layer is formed on the second sacrificial layer, and a second hardmask layer is formed on the first hardmask layer and patterned. The first hardmask layer is laterally recessed in a lateral direction under the second hardmask layer. The first and second sacrificial layers are etched to a corresponding width of the first hardmask layer. A spacer layer is formed on the fin, the first sacrificial layer, second sacrificial layer, the first hardmask layer and the second hardmask layer. The spacer layer is etched until it remains on a sidewall of the first sacrificial layer, the second sacrificial layer and the first hardmask layer, wherein the first and second sacrificial layers form the dummy gate.