Semiconductor structures having increased channel strain using fin release in gate regions
US9954083B2 · kind B2 · utility
1Cited by
9References
2Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 20, 2015 |
| Grant date | Apr 24, 2018 |
| Priority date | — |
| Expiry date | Aug 30, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of introducing strain in a channel region of a FinFET device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the FinFET device so as to release the upper portion of the fin structure from the substrate in the channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.