Methods for etching a metal layer to form an interconnection structure for semiconductor applications
US9960052B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2014 |
| Grant date | May 1, 2018 |
| Priority date | — |
| Expiry date | May 1, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76885
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention provide methods for patterning a metal layer, such as a copper layer, to form an interconnection structure in semiconductor devices. In one embodiment, a method of patterning a metal layer on a substrate includes (a) supplying an etching gas mixture comprising a hydro-carbon gas into a processing chamber having a substrate disposed therein, the substrate having a metal layer disposed thereon, (b) exposing the metal layer to an ashing gas mixture comprising a hydrogen containing gas to the substrate, and (c) repeatedly performing steps (a) and (b) until desired features are formed in the metal layer. During the patterning process, the substrate temperature may be controlled at greater than 50 degrees Celsius.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.