Aligning conductive vias with trenches
US9972533B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2017 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | Aug 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/528
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming conductive contacts on a wafer comprises forming a first hardmask, planarizing layer, second hardmask, and a layer of sacrificial mandrel material, and removing portions of the layer of sacrificial mandrel material to expose portions of the second hardmask and form a first and second sacrificial mandrel. Spacers are formed adjacent to the sacrificial mandrels. A filler material is deposited on the second hardmask, and a first mask is formed on the filler material. An exposed portion of the second sacrificial mandrel is removed to form a first cavity. The depth of the first cavity is increased. The first mask, portions of the first and second sacrificial mandrels, the filler material, portions of the second hardmask, the spacers, portions of the planarization layer and the first hardmask are removed. A second cavity is formed and the first and second cavities are filled with a conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.