Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of V0 via opens

US9905487B1 · kind B1 · utility

Assignee

• PDF SOLUTIONS, INC. · US

Inventors

• Stephen Lam · Merced, US
• Dennis Ciplickas · San Jose, US
• Tomasz Brozek · معلمی نژاد, US
• Jeremy Cheng · San Jose, US
• Simone Comensoli · Gandino, IT
• Indranil De · Alameda, US
• Kelvin Doong · Hsinchu, TW
• Hans Eisenmann · Tutzing, DE
• Timothy Fiscus · Beaver, US
• Jonathan Haigh · Pittsburgh, US
• Christopher Hess · Belmont, US
• John Kibarian · Los Altos Hills, US
• Sherry Lee · San Jose, US
• Marci Liao · Santa Clara, US
• Sheng-Che Lin · Hsinchu, TW
• Hideki Matsuhashi · Santa Clara, US
• Kimon Michaels · Monte Sereno, US
• Conor O'Sullivan · Campbell, US
• Markus Rauscher · Munich, DE
• Vyacheslav Rovner · Pittsburgh, US
• Andrzej Strojwas · Pittsburgh, US
• Marcin Strojwas · Pittsburgh, US
• Carl Taylor · Pittsburgh, US
• Rakesh Vallishayee · Dublin, US
• Larg Weiland · Hollister, US
• Nobuharu Yokoyama · Tokyo, JP

Key dates

• Filing date: Sep 28, 2016
• Grant date: Feb 27, 2018
• Expiry date: Sep 28, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/987
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Improved processes for manufacturing semiconductor wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements (“NCEM”) of fill cells that contain structures configured to target/expose a variety of open-circuit, short-circuit, leakage, and/or excessive resistance failure modes. Such processes include evaluating one or more Designs of Experiments (“DOEs”), each comprised of multiple NCEM-enabled fill cells, in at least two variants, targeted to the same failure mode. Such DOEs include multiple means/steps for enabling non-contact (NC) detection of V0 via opens.