Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells

US9922968B1 · kind B1 · utility

Assignee

• PDF SOLUTIONS, INC. · US

Inventors

• Stephen Lam · Merced, US
• Dennis Ciplickas · San Jose, US
• Tomasz Brozek · معلمی نژاد, US
• Jeremy Cheng · San Jose, US
• Simone Comensoli · Gandino, IT
• Indranil De · Alameda, US
• Kelvin Doong · Hsinchu, TW
• Hans Eisenmann · Tutzing, DE
• Timothy Fiscus · Beaver, US
• Jonathan Haigh · Pittsburgh, US
• Christopher Hess · Belmont, US
• John Kibarian · Los Altos Hills, US
• Sherry Lee · San Jose, US
• Marci Liao · Santa Clara, US
• Sheng-Che Lin · Hsinchu, TW
• Hideki Matsuhashi · Santa Clara, US
• Kimon Michaels · Monte Sereno, US
• Conor O'Sullivan · Campbell, US
• Markus Rauscher · Munich, DE
• Vyacheslav Rovner · Pittsburgh, US
• Andrzej Strojwas · Pittsburgh, US
• Marcin Strojwas · Pittsburgh, US
• Carl Taylor · Pittsburgh, US
• Rakesh Vallishayee · Dublin, US
• Larg Weiland · Hollister, US
• Nobuharu Yokoyama · Tokyo, JP

Key dates

• Filing date: Mar 31, 2017
• Grant date: Mar 20, 2018
• Expiry date: Mar 31, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/988
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of side-to-side shorts, and the second DOE contains fill cells configured to enable NC detection of chamfer shorts. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured.