Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

US9929063B1 · kind B1 · utility

Assignee

• PDF SOLUTIONS, INC. · US

Inventors

• Stephen Lam · Merced, US
• Dennis Ciplickas · San Jose, US
• Tomasz Brozek · معلمی نژاد, US
• Jeremy Cheng · San Jose, US
• Simone Comensoli · Gandino, IT
• Indranil De · Alameda, US
• Kelvin Doong · Hsinchu, TW
• Hans Eisenmann · Tutzing, DE
• Timothy Fiscus · Beaver, US
• Jonathan Haigh · Pittsburgh, US
• Christopher Hess · Belmont, US
• John Kibarian · Los Altos Hills, US
• Sherry Lee · San Jose, US
• Marci Liao · Santa Clara, US
• Sheng-Che Lin · Hsinchu, TW
• Hideki Matsuhashi · Santa Clara, US
• Kimon Michaels · Monte Sereno, US
• Conor O'Sullivan · Campbell, US
• Markus Rauscher · Munich, DE
• Vyacheslav Rovner · Pittsburgh, US
• Andrzej Strojwas · Pittsburgh, US
• Marcin Strojwas · Pittsburgh, US
• Carl Taylor · Pittsburgh, US
• Rakesh Vallishayee · Dublin, US
• Larg Weiland · Hollister, US
• Nobuharu Yokoyama · Tokyo, JP

Key dates

• Filing date: Sep 30, 2017
• Grant date: Mar 27, 2018
• Expiry date: Sep 30, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/20
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A process for making an integrated circuit, either in the form of a wafer, die, or chip, includes instantiating multiple standard cell-compatible fill cells, configured to enable non-contact electrical measurements. Such instantiated fill cells include mesh pads that contain at least three conductive stripes disposed between adjacent gate stripes. Such instantiated fill cells further include geometry to enable non-contact evaluation of Tip-to-Side shorts and/or leakages.