Method of manufacturing a device with MOS transistors
US9876032B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 18, 2016 |
| Grant date | Jan 23, 2018 |
| Priority date | — |
| Expiry date | Oct 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8325
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.