Philippe Flatresse
8Patents
3h-index
16Co-inventors
50Inventor score
Filing activity: May 29, 2003 → Dec 13, 2013
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8482070B1 | Silicon-on-insulator CMOS integrated circuit with multiple threshold voltages and a method for designing the same | Electricity | 19 | Active |
| US9092590B2 | Method for generating a topography of an FDSOI integrated circuit | Physics | 6 | Active |
| US8570096B2 | Transistor substrate dynamic biasing circuit | Electricity | 3 | Active |
| US7622983B2 | Method and device for adapting the voltage of a MOS transistor bulk | Physics | 3 | Active |
| US6871330B2 | Method and device for characterizing a CMOS logic cell to be produced in a technology of the partially depleted silicon-on-insulator type | Physics | 2 | Expired |
| US7847623B2 | Device and method for power switch monitoring | Electricity | 1 | Active |
| US7619863B2 | Gated thyristor and related system and method | Electricity | 0 | Active |
| US9911737B2 | Integrated circuit comprising transistors with different threshold voltages | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.