Edge hump reduction faceplate by plasma modulation
US10100408B2 · kind B2 · utility
3Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2015 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | Jul 13, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J37/32449
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
Embodiments described herein relate to a faceplate for improving film uniformity. A semiconductor processing apparatus includes a pedestal, an edge ring and a faceplate having distinct regions with differing hole densities. The faceplate has an inner region and an outer region which surrounds the inner region. The inner region has a greater density of holes formed therethrough when compared to the outer region. The inner region is sized to correspond with a substrate being processed while the outer region is sized to correspond with the edge ring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.