Methods of forming an air gap adjacent a gate of a transistor and a gate contact above the active region of the transistor
US10211100B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2017 |
| Grant date | Feb 19, 2019 |
| Priority date | — |
| Expiry date | Apr 1, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One method includes performing an etching process to define a gate cavity that exposes an upper surface and at least a portion of the sidewalls of a gate structure and forming a replacement spacer structure adjacent the exposed sidewalls of the gate structure, wherein the replacement spacer structure exposes a portion of the upper surface of the gate structure and includes at least one air space. In this example, the method also includes forming a conformal etch stop layer and a replacement gate cap structure in the gate cavity, selectively removing a portion of the replacement gate cap structure and a portion of the conformal etch stop layer so as to thereby expose the upper surface of the gate structure, and forming a conductive gate contact structure (CB) in the conductive gate contact opening, wherein the entire conductive gate contact structure (CB) is positioned vertically above the active region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.