Vertical field effect transistor formation with critical dimension control
US10217846B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2018 |
| Grant date | Feb 26, 2019 |
| Priority date | — |
| Expiry date | Jan 17, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are a method of forming vertical field effect transistor(s) and the resulting structure. In the method, five semiconductor layers are formed in a stack by epitaxial deposition. The first and fifth layers are one semiconductor material, the second and fourth layers are another and the third layer is yet another. The stack is patterned into fin(s). Vertical surfaces of the second and fourth layers of the fin(s) are etched to form upper and lower spacer cavities and these cavities are filled with upper and lower spacers. Vertical surfaces of the third layer of the fin(s) are etched to form a gate cavity and this cavity is filled with a gate. Since epitaxial deposition is used to form the semiconductor layers, the thicknesses of these layers and thereby the heights of the spacer cavities and gate cavity and the corresponding lengths of the spacers and gate can be precisely controlled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.