Integrated circuit structure, gate all-around integrated circuit structure and methods of forming same

US10290549B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Ruilong Xie · Niskayuna, US
• Julien Frougier · Albany, US
• Min Gyu Sung · Yongsan-gu, KR
• Edward J. Nowak · South Burlington, US
• Nigel G. Cave · Austin, US
• Lars Liebmann · Poughquag, US
• Daniel Chanemougame · Niskayuna, US
• Andreas Knorr · Saratoga Springs, US

Key dates

• Filing date: Sep 5, 2017
• Grant date: May 14, 2019
• Expiry date: Sep 5, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B10/125

Abstract

The disclosure is directed to gate all-around integrated circuit structures, finFETs having a dielectric isolation, and methods of forming the same. The gate all-around integrated circuit structure may include a first insulator region within a substrate; a pair of remnant liner stubs disposed within the first insulator region; a second insulator region laterally adjacent to the first insulator region within the substrate; a pair of fins over the first insulator region, each fin in the pair of fins including an inner sidewall facing the inner sidewall of an adjacent fin in the pair of fins and an outer sidewall opposite the inner sidewall; and a gate structure substantially surrounding an axial portion of the pair of fins and at least partially disposed over the first and second insulator regions, wherein each remnant liner stub is substantially aligned with the inner sidewall of a respective fin of the pair of fins.