Method for forming dual-deck channel hole structure of three-dimensional memory device
US10515975B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2018 |
| Grant date | Dec 24, 2019 |
| Priority date | — |
| Expiry date | Jul 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32134
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a channel hole structure of a 3D memory device is disclosed. The method includes: forming a first alternating dielectric stack and a first insulating layer on a substrate; forming a first channel structure in a first channel hole penetrating the first insulating layer and the first alternating dielectric stack; forming a sacrificial inter-deck plug in the first insulating layer; forming a second alternating dielectric stack on the sacrificial inter-deck plug; forming a second channel hole penetrating the second alternating dielectric stack and expose a portion of the sacrificial inter-deck plug; removing the sacrificial inter-deck plug to form a cavity; and forming an inter-deck channel plug in the cavity and a second channel structure in the second channel hole, the inter-deck channel plug contacts the first channel structure and the second channel structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.