Memory device with multiple memory arrays to facilitate in-memory computation

US10565138B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Jack T. Kavalieros · Portland, US
• Ram Krishnamurthy · Portland, US
• Sasikanth Manipatruni · Ithaca, US
• Gregory K. Chen · Ann Arbor, US
• Van H. Le · Portland, US
• Amrita Mathuriya · Portland, US
• Abhishek A. Sharma · Hillsboro, US
• Raghavan Kumar · Hillsboro, US
• Phil Knag · Portland, US
• Huseyin Ekin Sumbul · Portland, US
• Ian A. Young · Portland, US

Key dates

• Filing date: Sep 28, 2018
• Grant date: Feb 18, 2020
• Expiry date: Sep 28, 2038

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Techniques and mechanisms for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation, the first memory array receives the data from a second memory array of the memory device. The second memory array extends horizontally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.