FinFET structure with dielectric bar containing gate to reduce effective capacitance, and method of forming same

US10797049B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Hui Zang · Guilderland, US
• Haiting Wang · Clifton Park, US
• Chung Foong Tan · Singapore, SG
• Guowei Xu · Lawrence, US
• Ruilong Xie · Niskayuna, US
• Scott Beasor · Greenwich, US
• Liu Jiang · Clifton Park, US

Key dates

• Filing date: Oct 25, 2018
• Grant date: Oct 6, 2020
• Expiry date: Oct 25, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0135

Abstract

A FinFET structure having reduced effective capacitance and including a substrate having at least two fins thereon laterally spaced from one another, a metal gate over fin tops of the fins and between sidewalls of upper portions of the fins, source/drain regions in each fin on opposing sides of the metal gate, and a dielectric bar within the metal gate located between the sidewalls of the upper portions of the fins, the dielectric bar being laterally spaced away from the sidewalls of the upper portions of the fins within the metal gate.