Memory cell structure of a three-dimensional memory device
US10847528B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2020 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | Apr 13, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.