Data prefetching for graphics data processing

US11409658B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Vikranth Vemulapalli · Folsom, US
• Lakshminarayanan Striramassarma · Folsom, US
• Mike B. Macpherson · Portland, US
• Aravindh Anantaraman · Folsom, US
• Ben J. Ashbaugh · Folsom, US
• Murali Ramadoss · Folsom, US
• William Sadler · Folsom, US
• Jonathan Pearce · Hillsboro, US
• Scott Janus · Rocklin, US
• Brent Insko · Portland, US
• Vasanth Ranganathan · Cameron Park, US
• Kamal Sinha · Rancho Cordova, US
• Arthur Hunter · Cameron Park, US
• Prasoonkumar Surti · Folsom, US
• Nicolas C. Galoppo Von Borries · Portland, US
• Joydeep Ray · Folsom, US
• Abhishek R. Appu · Cameron Park, US
• Elmoustapha Ould-Ahmed-Vall · Chandler, US
• Altug Koker · Cameron Park, US
• SungYe Kim · Folsom, US
• Subramaniam Maiyuran · Citrus, US
• Valentin Andrei · San Jose, US

Key dates

• Filing date: Jan 28, 2021
• Grant date: Aug 9, 2022
• Expiry date: Jan 28, 2041

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.