Vertically stacked CMOS with upfront M0 interconnect

US11482621B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Willy Rachmady · Beaverton, US
• Patrick Morrow · Portland, US
• Aaron D. Lilak · Beaverton, US
• Rishabh Mehandru · Portland, US
• Cheng-Ying Huang
• Gilbert Dewey · Beaverton, US
• Kimin Jun · Hillsboro, US
• Ryan Keech · Portland, US
• Anh Phan · Beaverton, US
• Ehren Mannebach · Beaverton, US

Key dates

• Filing date: Sep 26, 2018
• Grant date: Oct 25, 2022
• Expiry date: Feb 25, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D88/01
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments include transistor devices and a method of forming the transistor devices. A transistor device includes a first dielectric over a substrate, and vias on a first metal layer, where the first metal layer is on an etch stop layer that is on the first dielectric. The transistor device also includes a second dielectric over the first metal layer, vias, and etch stop layer, where the vias include sidewalls, top surfaces, and bottom surfaces, and stacked transistors on the second dielectric and the top surfaces of the vias, where the sidewalls and top surfaces of the vias are positioned within a footprint of the stacked transistors. The stacked transistors include gate electrodes and first and second transistor layers. The first metal layer includes conductive materials including tungsten or cobalt. The footprint may include a bottom surface of the first transistor layer and a bottom surface of the gate electrodes.