Enhancing performance of overlay metrology
US11592755B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2021 |
| Grant date | Feb 28, 2023 |
| Priority date | — |
| Expiry date | Mar 31, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N23/45
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for metrology includes directing at least one illumination beam to illuminate a semiconductor wafer on which at least first and second patterned layers have been deposited in succession, including a first target feature in the first patterned layer and a second target feature in the second patterned layer, overlaid on the first target feature. A sequence of images of the first and second target features is captured while varying one or more imaging parameters over the sequence. The images in the sequence are processed in order to identify respective centers of symmetry of the first and second target features in the images and measure variations in the centers of symmetry as a function of the varying image parameters. The measured variations are applied in measuring an overlay error between the first and second patterned layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.