Method of 3D logic fabrication to sequentially decrease processing temperature and maintain material thermal thresholds

US11764113B2 · kind B2 · utility

Assignee

• TOKYO ELECTRON LIMITED · JP

Inventors

• Jeffrey Smith · Clifton Park, US
• Daniel Chanemougame · Niskayuna, US
• Lars Liebmann · Poughquag, US
• Paul Gutwin · Williston, US
• Robert D. Clark · Norman, US
• Anton J. deVilliers · Boise, US

Key dates

• Filing date: Aug 3, 2021
• Grant date: Sep 19, 2023
• Expiry date: Aug 3, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0179
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Techniques herein include methods for fabricating CFET devices. The methods enable high-temperature processes to be performed for FINFET and gate all around (GAA) technologies without degradation of temperature sensitive materials within the device and transistors. In particular, high temperature anneals and depositions can be performed prior to deposition of temperature-sensitive materials, such as work function metals and silicides. The methods enable at least two transistor devices to be fabricated in a stepwise manner while preventing thermal violations of any materials in either transistor.