Patent · US Active

Dynamic memory reconfiguration

US11954062B2 · kind B2 · utility

0Cited by

83References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Joydeep Ray · Folsom, US
Niranjan L. Cooray · Folsom, US
Subramaniam Maiyuran · Citrus, US
Altug Koker · Cameron Park, US
Prasoonkumar Surti · Folsom, US
Varghese George · Folsom, US
Valentin Andrei · San Jose, US
Abhishek R. Appu · Cameron Park, US
Guadalupe J. Garcia · Chandler, US
Pattabhiraman K · Bengaluru, IN
SungYe Kim · Folsom, US
Sanjay Kumar · Hillsboro, US
Pratik M. Marolia · Hillsboro, US
Elmoustapha Ould-Ahmed-Vall · Chandler, US
Vasanth Ranganathan · Cameron Park, US
William Sadler · Folsom, US
Lakshminarayanan Striramassarma · Folsom, US

Key dates

Filing date	Mar 14, 2020
Grant date	Apr 9, 2024
Priority date	—
Expiry date	Sep 9, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG06T15/06
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.