Sparse optimizations for a matrix accelerator architecture
US12293431B2 · kind B2 · utility
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Key dates
| Filing date | May 2, 2023 |
| Grant date | May 6, 2025 |
| Priority date | — |
| Expiry date | May 2, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to detect zero value elements within a vector or a set of packed data elements output by a processing resource and generate metadata to indicate a location of the zero value elements within the plurality of data elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.