Self-aligned method for vertical recess for 3D device integration

US12336274B2 · kind B2 · utility

Assignee

• TOKYO ELECTRON LIMITED · JP

Inventors

• Jeffrey Smith · Clifton Park, US
• Daniel Chanemougame · Niskayuna, US
• Lars Liebmann · Poughquag, US
• Paul Gutwin · Williston, US
• Subhadeep Kal · Albany, US
• Kandabara Tapily · Mechanicville, US
• Anton J. deVilliers · Boise, US

Key dates

• Filing date: Aug 1, 2022
• Grant date: Jun 17, 2025
• Expiry date: Dec 28, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/822
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Aspects of the present disclosure provide a self-aligned microfabrication method, which can include providing a substrate having vertically arranged first and second channel structures, forming first and second sacrificial contacts to cover ends of the first and second channel structures, respectively, covering the first and second sacrificial contacts with a fill material, recessing the fill material such that the second sacrificial contact is at least partially uncovered while the first sacrificial contact remains covered, replacing the second sacrificial contact with a cover spacer, removing a remaining portion of the first fill material, uncovering the end of the first channel structure, forming a first source/drain (S/D) contact to cover the end of the first channel structure, covering the first S/D contact with a second fill material, uncovering the end of the second channel structure, and forming a second S/D contact at the end of the second channel structure.