Gate-cut and separation techniques for enabling independent gate control of stacked transistors

US12336294B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Ruilong Xie · Niskayuna, US
• Nicolas Loubet · Guilderland, US
• Julien Frougier · Albany, US
• Lawrence A. Clevenger · Saratoga Springs, US
• Prasad Bhosale · Slingerlands, US
• Junli Wang · Slingerlands, US
• Balasubramanian Pranatharthiharan · Watervliet, US
• Dechao Guo · Niskayuna, US

Key dates

• Filing date: Nov 10, 2021
• Grant date: Jun 17, 2025
• Expiry date: Oct 18, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0172
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

Embodiments of the invention include vertically stacked field-effect transistors (FETs). The vertically stacked FETs include at least one first transistor and at least one second transistor separated by a dielectric isolation layer. Gate material is adjacent to the at least one first transistor and the at least one second transistor, at least one first height vertical layer being adjacent to and about a height of the gate material, at least one second height vertical layer being adjacent to and less than the height of the gate material.