Dynamic memory reconfiguration
US12386779B2 · kind B2 · utility
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104References
20Claims
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Key dates
| Filing date | Feb 5, 2024 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Feb 5, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.